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Video and Image Processing Suite UserGuideSubscribeSend FeedbackUG-VIPSUITE2015.05.04101 Innovation DriveSan Jose, CA 95134www.altera.com

Device Family SupportThe table below lists the device support information for the Video and Image Processing Suite IP cores.Table 1-3: Device Family S

Address Register Description1 Status• Bit 0 of this register is the Status bit.• This bit is asserted when the CVO IP core is producingdata.• Bit 1 of

Address Register Description10 Mode1 HorizontalSync LengthVideo mode 1 horizontal synchronization length. Specifies thelength of the horizontal synchr

Address Register Description27 Mode1 F0 AncillaryLineThe line in field F0 to start inserting ancillary data packets.28 Mode1 Valid Video mode 1 valid.

Address Register Description2 Interrupt Bits 2 and 1 are the interrupt status bits:• When bit 1 is asserted, the status update interrupt hastriggered.

Address Register Description15 Mode1 F0 VerticalFront PorchVideo mode 1 field 0 vertical front porch (interlaced videoonly). Specifies the length of t

Note: For the Clocked Video Output IP cores, to ensure the vid_f signal rises at the Field 0 blankingperiod and falls at the Field 1, use the followin

2D FIR Filter IP Core52015.05.04UG-VIPSUITESubscribeSend FeedbackThe 2D FIR Filter IP core performs 2D convolution using matrices of 3×3, 5×5, or 7×7

Coefficient PrecisionThe 2D FIR Filter IP core requires a fixed point type to be defined for the coefficients.The user-entered coefficients (shown as

Parameter Value DescriptionInput data type: Bits per pixelper color plane4-20, Default = 8 Select the number of bits per pixel (per colorplane).Note:

Parameter Value DescriptionOutput data type: Min 1,048,575 to -524,288,Default = 0Set output range minimum value.Note: The output is constrained to fa

LatencyYou can use the latency information to predict the approximate latency between the input and the outputof your video processing pipeline.The la

Signal Direction Descriptiondin_ready Output din_N port Avalon-ST ready signal. The IP core assertsthis signal when it is able to receive data.din_sta

Address Register Descriptionn Coefficient n The coefficient at position:• Row (where 0 is the top row of the kernel) is the integervalue through the t

Video Mixing IP Cores62015.05.04UG-VIPSUITESubscribeSend FeedbackThe Video Mixing IP cores mix together multiple image layers .This run-time control i

background layer. The IP core treats the non-image data packets from the foreground layers differentlydepending on their type.• Control packets (type

at the system-level if erroneous pixels have to be discarded. The IP core ignores all non-image datapackets (including control packets) and discards t

Parameter Value DescriptionNumber of color planes inparallel1, 2, 3 Select the number of color planes in parallel.Number of layers being mixed 2–12 Se

Parameter Value DescriptionPattern• Color bars• UniformbackgroundSelect the pattern you want to use for thebackground test pattern layer.Uniform value

Signal Direction Descriptiondin_N_valid Input din_N port Avalon-ST valid signal. This signal identifiesthe cycles when the port must input data.dout_N

Signal Direction Descriptioncontrol_read Output control slave port Avalon-MM read signal. When youassert this signal, the control port produces new da

Signal Direction Descriptiondout_N_ready Input dout_N port Avalon-ST ready signal. The downstreamdevice asserts this signal when it is able to receive

IP Core Mode LatencyClocked Video Input II• Synchronization signals:Embedded in video• Video in and out use thesame clock: On10 cycles• Synchronizatio

Table 6-7: Mixer II Control Register MapThe table below describes the control register map for Mixer II IP core.Address Register Description0 Control

Address Register Description20 Input 3 enable• Set to bit 0 to enable Input 3.• Set to bit 1 to enable consume mode.21 Reserved Reserved for future us

Chroma Resampler IP Core72015.05.04UG-VIPSUITESubscribeSend FeedbackThe Chroma Resampler IP core resamples video data to and from common sampling form

Figure 7-1: Resampling 4.4.4 to a 4.2.2 ImageThe figure below shows the location of samples in a co-sited 4:2:2 image.1 23412Sample No5 678++++++++34=

Figure 7-2: 4:2:2 Data at an Edge TransitionThe figure below shows 4:2:2 data at an edge transition. Without taking any account of the luma, theinterp

Note: All input data samples must be in unsigned format. If the number of bits per pixel per color planeis N, this means that each sample consists of

Chroma Resampler SignalsTable 7-2: Chroma Resampler SignalsSignal Direction Descriptionclock Input The main system clock. The IP core operates on the

Video Clipping IP Cores82015.05.04UG-VIPSUITESubscribeSend FeedbackThe Video Clipping IP cores clip video streams. You can configure these IP cores at

Parameter Value DescriptionNumber of color planes inparallel1–3, Default = 1 Select the number of color planes in parallel.Include Avalon-MM interface

Table 8-2: Clipper II Parameter SettingsParameter Value DescriptionMaximum input frame width 32–4096, Default =1920Specify the maximum frame width of

IP Core Mode LatencyDeinterlacer• Method: Bob• Frame buffering: NoneO (cycles)• Method: Motion-adaptive orWeave• Frame buffering: Double ortriple buff

Parameter Value DescriptionRight offset 0–1080, Default = 10 Specify the x coordinate for the right edge ofthe clipping rectangle. 0 is the right edge

Signal Direction Descriptiondout_endofpacket Output dout port Avalon-ST endofpacket signal. This signalmarks the end of an Avalon-ST packet.dout_ready

Signal Direction Descriptioncontrol_byteenable Input control slave port Avalon-MM byteenable bus. This busenables specific byte lane or lanes during t

Address Register Description2 Left Offset The left offset, in pixels, of the clipping window/rectangle.Note: The left and right offset values must be

Address Register Description4 Right Offset orWidthIn clipping window mode, the right offset of the window. Inclipping rectangle mode, the width of the

Color Plane Sequencer IP Core92015.05.04UG-VIPSUITESubscribeSend FeedbackThe Color Plane Sequencer IP core changes how color plane samples are transmi

Figure 9-1: Example of Combining Color PatternsThe figure shows an example of combining and rearranging two color patterns.Color pattern of a video da

data. Altera recommends that when you define a packet type where the length is variable andmeaningful, you send the length at the start of the packet.

Subsampled DataIn addition to fully sampled color patterns, the Color Plane Sequencer IP core also supports 4:2:2subsampled data.For the Color Plane S

Parameter Value Descriptiondout0: Color planes in parallel 1, 2, 3, 4 Select the number of color planes in parallelfor input port dout0.dout0: Halve c

IP Core Mode LatencyBroadcast Deinterlacer• Method: Motion-adaptive• Frame buffering: None• Output frame rate: As inputfield rate1 field + 2 lines• Me

Signal Direction Descriptionreset Input The IP core asynchronously resets when this signal is high.You must deassert this signal synchronously to the

Color Space Conversion IP Cores102015.05.04UG-VIPSUITESubscribeSend FeedbackThe Color Space Conversion IP cores transform video data between color spa

National Television System Committee (NTSC) systems or the Y'UV (luminance-bandwidth-chrominance) color model for Phase Alternation Line (PAL) sy

If the channels are in sequence, din_0 is first, then din_1, and din_2. If the channels are in parallel, din_0occupies the least significant bits of t

Color Space Conversion Parameter SettingsTable 10-1: Color Space Converter Parameter SettingsParameter Value DescriptionGeneralColor plane configurati

Parameter Value DescriptionGeneralRemove fraction bits by• Round values - Halfup• Round values - Halfeven• Truncate values tointegerSelect the method

OperandsCoefficient and summandsA0, B0, C0, S0A1, B1, C1, S1A2, B2, C2, S212 fixed-point values Each coefficient or summand is representedby a white c

Parameter Value DescriptionGeneralMaximum input frame height 32–4096,Default = 1080Specify the maximum height of input imagesor video frames in pixels

Parameter Value DescriptionGeneralConvert from signed to unsignedby• Saturating tominimum value atstage 4• Replacing negativewith absolute valueSelect

Signal Direction Descriptiondin_endofpacket Input din port Avalon-ST endofpacket signal. This signalmarks the end of an Avalon-ST packet.din_ready Out

Table 1-5: Performance and Resource Data Using Arria V DevicesThe following data are obtained through a 4K test design example using an Arria V device

Signal Direction Descriptioncontrol_byteenable Output control slave port Avalon-MM byteenable bus. This busenables specific byte lane or lanes during

Address Register Description2 Coefficient A0 The coefficient and summand registers use integer, signed 2’scomplement numbers. Refer to Color Space Con

Address Register Description4 Coefficient A0 The coefficient and summand registers use integer, signed 2’scomplement numbers. Refer to Color Space Con

Control Synchronizer IP Core112015.05.04UG-VIPSUITESubscribeSend FeedbackThe Control Synchronizer IP core synchronizes the configuration change of IP

Using the Control Synchronizer IP CoreThe example illustrates how the Control Synchronizer IP Core is set to trigger on the changing of thewidth field

Figure 11-2: Changing Video WidthTest PatternGeneratorFrameBufferControlSynchronizerScalerNios II CPURed Line Indicates Control Data Packet and Video

Figure 11-4: Reconfigured Scaler IITest PatternGeneratorFrameBufferControlSynchronizerScalerNios II CPURed Line Indicates Control Data Packet and Vide

Control Synchronizer SignalsTable 11-2: Control Synchronizer SignalsSignal Direction Descriptionclock Input The main system clock. The IP core operate

Signal Direction Descriptionslave_av_writedata Input slave port Avalon-MM writedata bus. The IP core usesthese input lines for write transfers.status_

Address Register Description3 Disable Trigger• Setting this register to 1 disables the trigger condition ofthe control synchronizer.• Setting this reg

Table 1-6: Performance and Resource Data Using Cyclone V DevicesThe following data are obtained through a video design example using a Cyclone V devic

Deinterlacing IP Cores122015.05.04UG-VIPSUITESubscribeSend FeedbackThe Deinterlacing IP cores provide deinterlacing algorithms.Interlaced video is com

IP Cores FeatureBroadcast Deinterlacer• Converts interlaced video to progressive video usinghigh quality motion-adaptive algorithm. This algorithmenha

Bob with Scanline DuplicationThe bob with scanline duplication algorithm is the simplest and cheapest in terms of logic.The bob with scanline duplicat

missing in the current field by calculating a function of other pixels in the current field and the threepreceding fields as shown in the following se

The motion-adaptive algorithm requires the buffering of two frames of data before it can produce anyoutput. The Deinterlacer always consumes the three

Pass-Through Mode for Progressive FramesIn its default configuration, the Deinterlacing IP cores discard progressive frames.Change this behavior if yo

Types DescriptionDouble-buffering• When you select double-buffering, external RAM uses two frame buffers.Input pixels flow through the input port and

If the external memory in your system runs at a different clock rate to the Deinterlacing IP cores, you canturn on an option to use a separate clock f

• Deinterlacer II processing 1080i60 input data• Phase 1: Read 2 lines = 1920 × 10 bits × 2 (YCbCr) × 2 × 1.0665 (inefficiency) = 81, 907.2 bits perli

When the bob algorithm is used and synchronization is done on a specific field (input frame rate = outputframe rate), the field that is constantly unu

IP Core Configuration ALM RAM DSPClocked VideoOutput• Number of color planes in parallel = 3• Sync signals = On separate wires• Pixel FIFO size = 1024

Parameter Value DescriptionMaximum image height 32–2600, Default = 480 Specify the maximum progressive frameheight in pixels. The maximum frame height

Parameter Value DescriptionFrame buffering mode• No buffering• Double buffering• Triple bufferingwith rate conversionSpecify whether to use external f

Parameter Value Description4:2:2 support for motionadaptive algorithmOn or Off Turn on to avoid color artefacts whenprocessing 4:2:2 Y'CbCr data

Parameter Value DescriptionMaximum packet length 10–1024, Default = 10 Select the maximum packet length as anumber of symbols. The minimum value is10

Parameter Value DescriptionAlign read/write bursts withburst boundariesOn or Off Turn on to avoid initiating read and writebursts at a position that w

Parameter Value DescriptionRun-time control On or Off Turn on to enable run-time control for thecadence detection and reverse pulldown.• Deinterlacer

Parameter Value DescriptionEDI read master FIFO depth 8–512, Default = 64 Select the FIFO depth of the edge-dependentinterpolation (EDI) Avalon-MM rea

Signal Direction Descriptiondin_valid Input din port Avalon-ST valid signal. This signal identifies thecycles when the port must enter data.dout_data

Signal Direction Descriptionma_control_av_write Input ma_control slave port Avalon-MM write signal. Whenyou assert this signal, the ma_control port ac

Signal Direction Descriptionwrite_master_av_write Output write_master port Avalon-MM write signal. The IP coreasserts this signal to indicate write re

IP Core Configuration ALM RAM DSPScaler II• Symbols in parallel = 3• Scaling algorithm = Polyphase• Enable run-time control of input/outputframe size

Signal Direction Descriptioncontrol_byteenable Output control slave port Avalon-MM byteenable bus. This busenables specific byte lane or lanes during

Signal Direction Descriptionma_read_master_waitrequest Input ma_read_master port Avalon-MM waitrequest signal.The system interconnect fabric asserts t

Signal Direction Descriptionmotion_write_master_burstcountOutput motion_write_master port Avalon-MM burstcountsignal. This signal specifies the number

Table 12-9: Deinterlacer Control Register Map for Synchronizing the Input and Output Frame RatesThe table below describes the control register map tha

Address Register Description4 Cadence detected• Reading a 1 from bit 0, indicates that the Deinterlacer II IPcore has detected a cadence and is perfor

Address Register RO/RW Description4 3:2 Cadence State(VOF State)RO Indicates overall 3:2 cadence state. May be a decoder todetermine whether the core

Address Register RO/RW Description12 Cadence Detect On RW• Setting the LSB of this register to 1 enables cadencedetection.• Setting the LSB of this re

Address Register RO/RW Description16 VOF Lock Delay RW Specifies the number of fields elapsed after the coredetects a cadence, but before reverse tele

Address Register RO/RW Description22 History MinimumValueRW The cadence bias for a given pixel. Setting a lower valuebiases the pixels toward film, an

Address Register RO/RW Description25 Motion Shift RW Specifies the amount of raw motion (SAD) data that isright-shifted. Shifting is used to reduce se

IP Core Stall Behavior Error Recovery2D FIR Filter• Has a delay of a little more than N–1lines between data input and output inthe case of a N×N 2D FI

Table 12-12: Suggested Register Settings For Altera UDX Reference DesignThe table below shows the suggested register settings for Altera’s High-Defini

Tuning Motion ShiftTo tune the motion shift register, follow these steps:1. Enable motion visualization; set Visualize Motion Values register to 1.2.

Frame Reader IP Core132015.05.04UG-VIPSUITESubscribeSend FeedbackThe Frame Reader IP core reads video frames stored in external memory and outputs the

width during compilation. Each word can only contain whole single-cycle color patterns. The wordscannot contain partial single-cycle color patterns. A

core, the Frame Reader IP core also has an interrupt that fires once per video data packet output, which isthe frame completed interrupt.Frame Reader

Signal Direction Descriptiondout_ready Input dout port Avalon-ST ready signal. The downstreamdevice asserts this signal when it is able to receive dat

Signal Direction Descriptionmaster_av_waitrequest Input master port Avalon-MM waitrequest signal. The systeminterconnect fabric asserts this signal to

Address Register Description11 Frame 1 Base Address The 32-bit base address of the frame.12 Frame 1 Words The number of words (reads from the master p

Frame Buffer IP Cores142015.05.04UG-VIPSUITESubscribeSend FeedbackThe Frame Buffer IP cores buffer video frames into external RAM.IP Cores FeatureFram

Figure 14-1: Frame Buffer Block DiagramMemoryWriterMemoryReaderAvalon-ST Input(din)Avalon-ST Output(dout)DDR2Arbitration LogicAvalon-MM Master(read_ma

ContentsVideo and Image Processing Suite Overview... 1-1Release Information...

IP Core Stall Behavior Error RecoveryAlpha BlendingMixer/Mixer IIAll modes stall for a few cycles after eachoutput frame and between output lines.Betw

• The writer uses one buffer to store input pixels.• The reader locks the second buffer that reads the output pixels from the memory.• The third buffe

The user packets are never repeated and they are not dropped as long as memory space is sufficient. Thecontrol packets are not stored in memory.• The

Frame Buffer Parameter SettingsTable 14-2: Frame Buffer Parameter SettingsParameter Value DescriptionMaximum image width 32–2600, Default = 640 Specif

Parameter Value DescriptionSupport for interlaced streams On or Off Turn on to support consistent dropping andrepeating of fields in an interlaced vid

Parameter Value DescriptionBase address of frame buffers Any 32-bit value,Default = 0×00000000Select a hexadecimal address of the framebuffers in exte

Parameter Value DescriptionWrite FIFO burst target 2–256,Default = 32Select the burst target for the write-only Avalon-MM interface.Read FIFO depth 16

Parameter Value DescriptionRun-time readercontrolOn or Off Run-time control for the read interface.Avalon-MM masterlocal ports width16–256,Default = 2

Signal Direction Descriptionread_master_av_clock Input read_master port clock signal. The interface operates onthe rising edge of the clock signal.rea

Table 14-5: Reader Control Interface Signals for Frame Buffer IP CoreThese signals are present only if you turned on the control interface for the rea

Signal Direction Descriptionmem_reset Input mem_master port reset signal. The interface asynchro‐nously resets when this signal is high. You must deas

IP Core Stall Behavior Error RecoveryChromaResamplerAll modes stall for a few cycles betweenframes and between lines.Latency from input to output vari

Signal Direction Descriptionmem_master_wr_address Output mem_master_wr port Avalon-MM address bus. This busspecifies a byte address in the Avalon-MM a

Address Register Description2 Frame Counter Read-only register updated at the end of each frame processedby the writer. The counter is incremented if

Table 14-10: Frame Buffer II Control Register Map for the WriterThe table below describes the control register map for the writer component.Note: Addr

Address Register Description2 Interrupt Bits 2 and 1 are the interrupt status bits:• When bit 1 is asserted, the status update interrupt hastriggered.

Gamma Corrector IP Core152015.05.04UG-VIPSUITESubscribeSend FeedbackThe Gamma Corrector IP core corrects video streams for the physical properties of

Gamma Corrector SignalsTable 15-2: Gamma Corrector SignalsSignal Direction Descriptionclock Input The main system clock. The IP core operates on the r

Signal Direction Descriptiongamma_lut_av_write Input gamma_lut slave port Avalon-MM write signal. Whenyou assert this signal, the reader control port

Address Register Description2 to 2N +1where N is thenumber of bitsper colorplane.Gamma Look-Up Table These registers contain a look-up table that is u

Interlacer IP Core162015.05.04UG-VIPSUITESubscribeSend FeedbackThe Interlacer IP core converts progressive video to interlaced video by dropping half

Interlacer Parameter SettingsTable 16-1: Interlacer Parameter SettingsParameter Value DescriptionMaximum image width 32–2600, Default = 640 Specify th

IP Core Stall Behavior Error RecoveryClocked VideoOutput/Clocked VideoOutput II• Dictated by outgoing video.• If its input FIFO is empty, duringhorizo

Signal Direction Descriptionreset Input The IP core asynchronously resets when this signal is high.You must deassert this signal synchronously to the

Signal Direction Descriptioncontrol_av_writedata Input control slave port Avalon-MM writedata bus. The IPcore uses these input lines for write transfe

Scaler II IP Core172015.05.04UG-VIPSUITESubscribeSend FeedbackThe Scaler II IP core resizes video streams, and supports nearest neighbor, bilinear, bi

For each output pixel, the nearest-neighbor method picks the value of the nearest input pixel to thecorrect input position. Formally, to find a value

precision of each error variable is determined by the number of fraction bits chosen by the user, Bfh andBfv, respectively.Their values can be calcula

Figure 17-1: Polyphase Mode Scaler Block DiagramThe figure below shows the flow of data through an instance of the Scaler II in polyphase mode.∑Cv0Bit

• Nv = vertical taps• Nh = horizontal taps• Bdata = bit width of the data samples• Bv = bit width of the vertical coefficients• Bh = bit width of the

Polyphase Algorithmic DescriptionThe algorithmic operations of the polyphase scaler can be modeled using a frame-based method.The filtering part of th

Figure 17-2: Lanczos 2 Function at Various PhasesThe figure below shows how a 2-lobe Lanczos-windowed sinc function (usually referred to as Lanczos 2)

Compile-time custom coefficients are loaded from a CSV file. One CSV file is specified for verticalcoefficients and one for horizontal coefficients. F

IP Core Stall Behavior Error RecoveryControlSynchronizer• Stalls for several cycles between packets.• Stalls when it enters a triggered statewhile it

• The sharpening filter is primarily for downscale, but you may also use it with upscale. You may enableor disable this functionality at runtime.• The

Parameter Value DescriptionNo blanking in video On or Off Turn on if the input video does not containvertical blanking at its point of conversion toth

Parameter Value DescriptionDefault upper blur limit (percolor plane)0 to 2bits per symbol–1,Default = 15Specify the default value for the blurred-edge

Parameter Value DescriptionHorizontal coefficient banks 1–32, Default = 1 Select the number of banks of horizontal filtercoefficients for polyphase al

Signal Direction Descriptiondin_valid Input din port Avalon-ST valid signal. This signal identifies thecycles when the port must enter data.dout_data

Signal Direction Descriptioncontrol_write Input control slave port Avalon-MM write signal. When youassert this signal, the control port accepts new da

Address Register Description6 Lower Blur Threshold Specifies the minimum difference between two pixels for ablurred edge to be detected between the pi

Video Switching IP Cores182015.05.04UG-VIPSUITESubscribeSend FeedbackThe Video Switching IP cores allow the connection of up to twelve input video str

Mixer Layer SwitchingLayer switching is the ability to change the layer that a video stream is on, moving it in front of or behindthe other video stre

Video Switching Parameter SettingsTable 18-2: Video Switching Parameter SettingsParameter Value DescriptionBits per pixel per color plane 4–20, Defaul

IP Core Stall Behavior Error RecoveryDeinterlacer II/BroadcastDeinterlacerStores input video fields in the externalmemory and concurrently uses these

Signal Direction Descriptiondin_N_endofpacket Input din_N port Avalon-ST endofpacket signal. This signalmarks the end of an Avalon-ST packet.din_N_rea

Signal Direction Descriptionalpha_out_N_ready Input alpha_out port Avalon-ST ready signal. The downstreamdevice asserts this signal when it is able to

Table 18-6: Switch II Control Register MapThe table below describes the control register map for Switch II IP core.Address Register Description0 Contr

Test Pattern Generator IP Cores192015.05.04UG-VIPSUITESubscribeSend FeedbackThe Test Pattern Generator IP cores generate a video stream that displays

Figure 19-1: Color Bar PatternThe sequence to produce a static image runs through the eight possible on or off combinations of thethree color componen

Color R'G'B' Y'CbCrGreen (16,180,16) (112,72,58)Magenta (180,16,180) (84,184,198)Red (180,16,16) (65,100,212)Blue (16,16,180) (35,

}}Test Pattern Generator Parameter SettingsTable 19-2: Test Pattern Generator Parameter SettingsParameter Value DescriptionRun-time control of image s

Table 19-3: Test Pattern Generator II Parameter SettingsParameter Value DescriptionRun-time control of image size On or Off Turn on to enable run-time

Test Pattern Generator SignalsTable 19-4: Test Pattern Generator SignalsSignal Direction Descriptionreset Input The IP core asynchronously resets when

Signal Direction Descriptiondout_startofpacket Output dout port Avalon-ST startofpacket signal. This signalmarks the start of an Avalon-ST packet.dout

IP Core Stall Behavior Error RecoveryFrame Buffer/Frame Buffer II• May stall frequently and read or writeless than once per clock cycle duringcontrol

Signal Direction Descriptiondout_data Output dout port Avalon-ST data bus. This bus enables thetransfer of pixel data out of the IP core.dout_endofpac

Address Register Description4 R/Y The value of the R (or Y) color sample when the test pattern isa uniform color background.Note: Available only when

Address Register Description5 R/Y The value of the R (or Y) color sample when the test pattern isa uniform color background.Note: Available only when

Trace System IP Core202015.05.04UG-VIPSUITESubscribeSend FeedbackThe Trace System IP core is a debugging and monitoring component.The trace system col

The IP core provides access to the control interfaces on the monitors. You can use these control ports tochange the capture settings on the monitors;

Trace System SignalsTable 20-2: Trace System SignalsSignal Direction Descriptionclk_clk Input All signals on the trace system are synchronous to thisc

Signal Direction Descriptioncapturen_startofpacket Input capturen port Avalon-ST startofpacket signal.This signal marks the start of an Avalon-ST pack

To start System Console, do one of the following steps:• Run system-console from the command line.• In Qsys, on the Tools menu, select Systems Debuggi

• In the System Console window, on the File menu, select Load Design. Open the Quartus II ProjectFile (.qpf) for your design.• From the System Console

Table 20-3: Functions of Trace Control Bar IconsThe table lists the trace control bar, which lets you control the acquisition of data through the trac

IP Core Stall Behavior Error RecoveryScaler II• The ratio of reads to writes isproportional to the scaling ratio andoccurs on both a per-pixel and a p

Command Arguments Functiontrace_get_monitor_info<open_service><monitor_id>Returns a serialized array containinginformation about the speci

Command Arguments Functiontrace_load<filename>Loads a trace database from disk. This returnsa new service path, which can be viewed as ifit is a

Avalon-ST Video Monitor IP Core212015.05.04UG-VIPSUITESubscribeSend FeedbackThe Avalon-ST Video Monitor IP core is a debugging and monitoring componen

Note: System Console uses the sopcinfo file (written by Qsys) or the .sof (written by the Quartus IIsoftware) to discover the connections between the

Statistics DescriptionUtilization [Data transfer cycles / (Data transfer cycles + Not ready andvalid cycles + Ready and not valid cycles + Not ready a

Parameter Value DescriptionColor planes transmitted inparallelOn or Off• Turn on to transmit all the color planes atthe same time in parallel.• Turn o

Signal Direction Descriptiondin_data Input din port Avalon-ST data bus. This bus enables thetransfer of pixel data into the IP core.din_endofpacket In

Signal Direction Descriptioncontrol_read Input control slave port Avalon-MM read signal. The IP coreasserts this signal to indicate read requests from

Address Register Description5 Control• Bits 15:0 control the linear feedback shift register (LFSR)mask for the pixel capture randomness function. Thel

Avalon-ST Video Verification IP SuiteA2015.05.04UG-VIPSUITESubscribeSend FeedbackThe Avalon-ST Video Verification IP Suite provides a set of SystemVer

IP Core Stall Behavior Error RecoveryEnabling run-time control of resolutionsaffects stalling between frames:• With no run-time control: about 10cycle

Although the test environment in the example shows a simple example of using the class library, other testenvironments can conform to this test struct

Figure A-2: UML-Style Class DiagramThe figure shows a unified modeling language (UML)-styled diagram of the class structure of the libraryand how thes

Table A-1: Class DescriptionThe table describes each of the classes in the av_st_video_classes package.Note: The classes listed do not contain informa

Class Descriptionclass c_av_st_video_controlParameterized class.Extends c_av_video_item. Comprises of width, height, andinterlaced bits (the fields fo

Class Descriptionclass c_av_st_video_source_bfm_’SOURCEExtends c_av_st_video_source_sink_base.Named according to the instance names of the Avalon-ST s

Class Descriptionclass c_av_st_video_file_ioParameterized class.Extends c_av_video_item. Comprises of width, height, andinterlaced bits (the fields fo

a. Copy the verification files to a local directory and cd to the testbench directory.>cp $(QUARTUS_ROOTDIR)/../ip/altera/vip/verification $ALTERA_

Figure A-4: tb.v Netlist2. Run the test by changing to the example video files test or example constrained random test directoryand start the QuestaSi

To generate the .avi file, open a DOS command prompt from a Windows machine and run thefollowing convertor utility:C:>raw2avi.exe vip_car_out.raw v

First, the test must define the numbers of bits per channel and channels per pixel, because most of theclasses require this information. Next, the cla

Interfaces22015.05.04UG-VIPSUITESubscribeSend FeedbackThe IP cores in the Video and Image Processing Suite use standard interfaces for data input and

and m_video_items_for_sink_bfm, each of type c_av_st_video_item. These shall be used to pass videoitems from the file reader into the source BFM and f

do begin video_file_writer.wait_for_and_write_video_packet_to_file(); end while ( video_file_writer.get_video_packet

Video Field Life CycleFigure A-5: Video Field Life CycleThe figure below shows the life cycle of the video field.AvalonSource BFM Video Source BFMVide

Stage DescriptionStage 3• The video source BFM retrieves the data from its mailbox, recasts the databack into a c_av_st_video_data video object, and b

Figure A-6: Example of a Constrained Random Test EnvironmentThe figure below shows the constrained random test environment structure.Avalon-ST Source

m_video_items_for_scoreboard.put(video_data_pkt2); end else if (r>34) begin video_cont

begin // Get the reference item from the scoreboard mailbox : m_video_items_for_scoreboard.get(ref_pkt);

grey = new (); grey.packet_type = video_packet; do begin grey_pixel = new(); rgb_pixel = rgb.pop_pixel();

Method Call Descriptionfunction t_packet_control get_append_garbage();—function int get_garbage_probability (); —function void set_width (bit [15:0] w

c_av_st_video_dataThe declaration for the c_av_st_video_data class:class c_av_st_video_data#(parameter BITS_PER_CHANNEL = 8,CHANNELS_PER_PIXEL = 3) ex

The Clocked Video Input and Clocked Video Output IP cores also have external interfaces that supportclocked video standards. These IP cores can connec

Table A-8: Method Calls for c_av_st_video_file_io ClassMethod Call Descriptionfunction void set_send_control_packets(t_packet_controls);If this method

Method Call Descriptionfunction void set_user_packet_probability (ints);If the send_user_packets is set to random,the user_packet_probability controld

Method Call Descriptionfunction void set_video_data_type(string s);Sets the fourcc[3] code associated with theraw video data. The following are thesup

Method Call Descriptiontask read_video_packet(); The main file reading method call. Binary datais read from the file and packed into pixelobjects acco

Member DescriptionInt late_eop_probability = 20; —int user_packet_probability = 20; —int control_packet_probability = 20; —mailbox #(c_av_st_video_ite

Table A-11: Members of c_av_st_video_item ClassMember Descriptiont_packet_types packet_type; Packet_type must be one of the following:• video_packet•

Table A-13: Members of c_av_st_video_source_sink_base ClassMember Descriptionmailbox # (c_av_st_video_item) m_video_items=new(0);The Avalon-ST video s

Table A-14: Method Calls for c_av_st_video_sink_bfm_’SINK ClassThis class does not have additional members to those of the base class.Method Call Desc

Method Call Descriptiontask send_video; The send_video() task waits until a videoitem is put into the mailbox, then it drives theAvalon-ST sink BFM&ap

Table A-17: Members of c_av_st_video_user_packet ClassMember Descriptionrand bit[BITS_PER_CHANNEL*CHANNELS_PER_PIXEL-1:0]data[$]User data is stored as

Modules for Clocked Video Input II IP Core...4-15Clocked Video In

Figure 2-2: Progressive Frame FormatVertical BlankingF0 Active PictureHorizontal BlankingHorizontal SyncVertical SyncWidthHeightUG-VIPSUITE2015.05.04V

width (160) = 0height (120) = 0Choose output colorspace:1.RGB2.YCbCr3.MONO1Choose output bps (8, 10)8Choose output interlacing:1.progressive2.interlac

Figure A-7: Supported FOURCC Codes and Data FormatThe figure below shows an example of the data format required by the file I/O class for each of thes

Choosing the Correct DeinterlacerB2015.05.04UG-VIPSUITESubscribeSend FeedbackYou should choose the right deinterlacer based on the quality of the outp

Figure B-2: Motion Adaptive Deinterlacing OptionThe figure below shows an example output from Motion Adaptive deinterlacing option.To enable this opti

With the moving Dial test sequence, the motion adaptive HQ mode improves the Bob interpolationfurther by operating on a 17×3 kernel of pixels. This al

Figure B-6: 3:2 Detection and 2:2 Detection ComparisonThe figure below shows the comparison between 3:2 and 2:2 detection.111223 33 442134567811 2233

Additional InformationC2015.05.04UG-VIPSUITESubscribeSend FeedbackAdditional information about the document and Altera.Document Revision HistoryDate V

Date Version Changes• Edited the parameter settings information for the Mixer II IP core.• Added description for new parameter Pattern which enables y

Date Version ChangesAugust 2014 14.0• Added new IP cores: Clocked Video Output II, Clocked Video InputII, Color Space Converter II, Mixer II, Frame Bu

Date Version ChangesJanuary 2013 12.1• Added Deinterlacer II Sobel-Based HQ Mode information for theDeinterlacer II IP core.• Updated Table 1–17 to in

Figure 2-3: Interlaced Frame FormatVertical BlankingF0 Active PictureHorizontal BlankingHorizontal SyncVertical SyncF0 Vertical BlankingF1 Active Pict

Date Version ChangesNovember20099.1• Added new IP cores: Frame Reader, Control Synchronizer, andSwitch.• The Frame Buffer IP core supports controlled

Clocked Video Output IP CoresFor the embedded synchronization format, the CVO IP cores insert the horizontal and vertical syncs andfield into the data

The CVI IP cores extract any ancillary packets from the Y channel during the vertical blanking. Ancillarypackets are not extracted from the horizontal

Figure 2-6: Separate Synchronization Signals Timing Diagramvid_de/vid_datavalid (1)D0 DNvid_data(1): vid_datavalid: Clocked Video Output IP core

Table 2-3: Avalon-ST Video Protocol ParametersParameter ValuesIP Cores Frame Width/HeightInterlaced/ProgressiveBits per ColorSampleColor Pattern2D FIR

Parameter ValuesIP Cores Frame Width/HeightInterlaced/ProgressiveBits per ColorSampleColor PatternDeinterlacer Run-timecontrolledInterlaced inputand p

Parameter ValuesIP Cores Frame Width/HeightInterlaced/ProgressiveBits per ColorSampleColor PatternInterlacer Run-timecontrolledProgressive;interlaced

Type Identifier Description13 Ancillary data packet14 Reserved for future Altera use15 Control data packetFigure 2-7: Packet Structure Start End Pack

Color PatternThe organization of the color plane samples within a video data packet is referred to as the color pattern.This parameter also defines th

Color Space Conversion Parameter Settings...10-4Color Space Con

Figure 2-10: Vertically Subsampled Y'CbCrThe figure below samples from the upper color plane transmitted on even rows and samples from thelower p

Parameter Recommended Color PatternsBits per Color Sample Parallel SequenceY’CbCrYCbCrCrCb Y4:2:2 Y’CbCrCb CrY YCrCb YYFollowing these recommendations

Structure of Video Data PacketsFigure 2-11: Parallel Color PatternThis figure shows the structure of a video data packet using a set parallel color pa

The width and height values are the dimensions of the video data packets that follow. The width refers tothe width in pixels of the lines of a frame.

ParametersDescriptionType Width Height Interlacing15 640 480 0000 The frames that follow are progressive with aresolution of 640×480. The frames were

Structure of a Control Data PacketA control data packet complies with the standard of a packet type identifier followed by a data payload.The data pay

Figure 2-15: One Symbol in ParallelControl data, reference numbers to Table 4-5 Control data packet type identifier(4 bits in least significant symbo

To make the protocol flexible and extensible, the Video and Image Processing IP cores obey the followingrules about propagating non-video packets:• Th

Signal Width Directionendofpacket 1 Source to SinkRelated InformationAvalon Interface SpecificationsProvides more information about these interface ty

Figure 2-16: Timing Diagram Showing R’G’B’ Transferred in ParallelThe figure below shows how the first few pixels of a frame are processed.clockdin_re

Gamma Corrector IP Core...15-1Gamma Corrector Parameter Settings...

ready latency in the Avalon Interface Specifications. All the Avalon-ST interfaces used by the Videoand Image Processing Suite IP cores have a ready l

Figure 2-17: Timing Diagram Showing R’G’B’ Transferred in SequenceThe figure shows how a number of pixels from the middle of a frame are processed.clo

Example 3 (Control Data Transfer)Figure 2-18: Timing Diagram Showing Control Packet TransferThis figure shows the transfer of a control packet for a f

The first two registers of every control interface perform the following two functions (the others vary witheach control interface):• Register 0 is th

You can build logic (or program a Nios II processor) to control the gamma corrector as follows:1. Set the Go bit to zero. This causes the IP core to s

Signal Width Directionwaitrequest 1 Outputirq(6)1 OutputNote: The list does not include clock and reset signal types. The Video and Image Processing S

Note: The clock and reset signal types are optional. The Avalon-MM master interfaces can operate on adifferent clock from the IP core and its other in

Getting Started32015.05.04UG-VIPSUITESubscribeSend FeedbackThe Video and Image Processing Suite IP cores are installed as part of the Quartus II insta

Specifying IP Core Parameters and OptionsFollow these steps to specify IP core parameters and options.1. In the Qsys IP Catalog (Tools > IP Catalog

Related Information• Altera Licensing Site• Altera Software Installation and Licensing ManualOpenCore Plus IP EvaluationAltera's free OpenCore Pl

Avalon-ST Video Monitor IP Core...21-1Packet Visualization...

Clocked Video Interface IP Cores42015.05.04UG-VIPSUITESubscribeSend FeedbackThe Clocked Video Interface IP cores convert clocked video formats (such a

Output IP cores still accept data on the Avalon-ST Video interface for as long as there is space in the inputFIFO.The sequence for starting the output

Format DescriptionPicture height (in lines)• The IP core counts the total number of lines per frame orfield, and the number of lines in the active pic

• Clocked Video Input IP coreAfter reset, if the IP core has not yet determined the format of the incoming video, it uses the valuesspecified under th

InterruptsThe CVI IP cores produce a single interrupt line.Table 4-5: Internal InterruptsThe table below lists the internal interrupts of the interrup

The CVO IP cores can be configured to support between 1 to 14 different modes and each mode has abank of registers that describe the output frame.• Cl

Figure 4-1: Progressive Frame ParametersThe figure shows how the register values map to the progressive frame format.Active samplesH backporchH blanki

Figure 4-2: Interlaced Frame ParametersThe figure shows how the register values map to the interlaced frame format.F0 active linesF1 active linesActiv

• For Clocked Video Output IP Core, the following steps reconfigure mode 1:1. Write 0 to the Mode1 Valid register.2. Write to the Mode 1 configuration

A CVI IP core can take in the locked PLL clock and the SOF signal and align the output video to thesesignals. This produces an output video frame that

Video and Image Processing Suite Overview12015.05.04UG-VIPSUITESubscribeSend FeedbackThe Altera® Video and Image Processing Suite collection of IP cor

Figure 4-3: Genlock Example ConfigurationThe figure shows an example of a Genlock configuration for Clocked Video Input IP core.524 00 1 0 11010SubSam

Note: For Clocked Video Output IP core, you can also read the current level of the FIFO from the UsedWords register. This register is not available fo

AFD Extractor (Clocked Video Input)When the output of the CVI IP cores connects to the input of the AFD Extractor, the AFD Extractorremoves any ancill

Figure 4-4: Ancillary Packet RegisterThe figure below shows the position of the ancillary packets. The different colors indicate differentancillary pa

Table 4-8: AFD Inserter Register MapAddress Register Description0 Control• When bit 0 is 0, the core discards all packets.• When bit 0 is 1, the core

Figure 4-5: Block Diagram for Clocked Video Input II IP CoreThe figure below shows a block diagram of the Clocked Video Input II IP core architecture.

Modules DescriptionResolution_detection• This module uses the h_sync, v_sync, de, and f signals to detect theresolution of the incoming video.• The re

Modules DescriptionAv_st_output• This module creates the control packets, from the detectedresolution read from the control module, and the video pack

Parameter Value DescriptionWidth 32–65,536, Default =1920Specify the image width to be used when noformat is automatically detected.Height – frame/fie

Parameter Value DescriptionSync signals• Embedded in video• On separate wiresSpecify whether to embed the synchroniza‐tion signal in the video stream

IP CoreFeature SupportPixels in Parallel 4:2:2 Support InterlacedClocked VideoOutput (CVO)No Yes YesClocked VideoOutput II (CVO II)Yes Yes YesColor Pl

Parameter Value DescriptionUse control port On or Off Turn on to use the optional stop/go controlport.Table 4-12: Clocked Video Output Parameter Setti

Parameter Value DescriptionFrame/Field 1: Ancillary packetinsertion line32–65536, Default = 0 Specify the line where ancillary packetinsertion starts.

Parameter Value DescriptionPixel FIFO size 32–(memory limit),Default = 1920Specify the required FIFO depth in pixels,(limited by the available on-chip

Parameter Value DescriptionAllow output of color planes insequenceOn or Off• Turn on if you want to allow run-timeswitching between sequential formats

Parameter Value DescriptionSeparate syncs only - Frame/Field 1: Vertical back porch32–65536, Default = 36 Specify the number of lines in the verticalb

Clocked Video Interface SignalsTable 4-14: Control Signals for CVI and CVO IP CoresSignal Direction Descriptionav_address Input control slave port Ava

Signal Direction Descriptionav_read Input control slave port Avalon-MM read signal. When youassert this signal, the control port drives new data ontot

Signal Direction Descriptionis_sop Output dout port Avalon-ST startofpacket signal. This signal isasserted when the IP core is starting a new frame.is

Signal Direction Descriptionvid_hd_sdn Input Clocked video color plane format selection signal. Thissignal distinguishes between sequential (when low)

Signal Direction Descriptiondout_valid Output dout port Avalon-ST valid signal. This signal is assertedwhen the IP core produces data.status_update_in

Release InformationThe following table lists information about this release of the Video and Image Processing Suite.Table 1-2: Release InformationItem

Signal Direction Descriptionvid_hd_sdn Input Clocked video color plane format selection signal . Thissignal distinguishes between sequential (when low

Signal Direction Descriptionis_eop Input dout port Avalon-ST endofpacket signal. This signal isasserted when the downstream device is ending a frame.i

Signal Direction Descriptionvid_f Output Clocked video field signal. For interlaced input, this signaldistinguishes between field 0 and field 1. For p

Table 4-19: Clocked Video Output II SignalsSignal Direction Descriptionmain_reset_reset Input The IP core asynchronously resets when you assert thissi

Signal Direction Descriptionstatus_update_int Output control slave port Avalon-MM interrupt signal. Whenasserted, the status registers of the IP core

Signal Direction Descriptionvid_trs Output Clocked video time reference signal (TRS) signal. Usedwith the SDI IP core to indicate a TRS, when asserted

Address Register Description1 Status• Bit 0 of this register is the Status bit.• This bit is asserted when the CVI IP core is producingdata.• Bits 5,

Address Register Description7 Total Sample Count The detected sample count of the video streams includingblanking.8 F0 Total Line Count The detected l

Address Register Description1 Status• Bit 0 of this register is the Status bit.• This bit is asserted when the CVI IP core is producingdata.• Bits 6–1

Address Register Description9 F1 Total Line Count The detected line count of the video streams F1 field includingblanking.10 Standard The contents of